1. Field of the Invention
The present invention relates in general to a variable rate modulator for generating a modulated output sequence at a fixed rate representing an input sequence received at a variable rate, and in particular to an interpolating root Nyquist filter for a variable rate modulator.
2. Description of Related Art
FIG. 1 illustrates in block diagram form a prior art a variable rate quadrature amplitude modulator 8 generally similar to modulator described in U.S. Pat. No. 6,421,396. Modulator 8 includes a baseband and symbol mapping block 10 for processing an incoming data sequence DIN arriving at a “data” rate fdata to produce a pair of digital symbol sequences xa(n) and xb(n) at a “symbol” rate fsymb wherefsymb=fdata/N  [1]Symbol sequences xa(n) and xb(n) collectively represent the data content of data sequence DIN. A pair of root Nyquist filters 12A and 12B low pass filter the xa(n) and xb(n) sequences to produce sequences ya(n) and yb(n) at twice the symbol rate, 2fsymb. A pair of interpolate by K filters 14 interpolate sequences ya(n) and yb(n) to generate sequences za(n) and zb(n) at a “sample” rate fsamp that is 2K times higher than the symbol rate fsymb of sequences ya(n) and yb(n):fsamp=2K·fsymb  [2]A circuit block 16 quadrature modulates and sums sequences za(n) and zb(n) to provide an output data sequence DOUT at the sample rate fsamp. A digital-to-analog converter 18 then converts sequence DOUT into an analog signal AOUT representing the data content of DIN.
The remote device (not shown) that supplies the input data sequence DIN also provides a clock signal CLK1 at the frequency of data rate fdata to clock data elements of the DIN sequence into block 10. A timing synchronizer 24 generates clock signal CLK2 at the frequency of the symbol rate fsymb to tell block 10 when to produce elements of the xa(n) and xb(n) sequences and generates a CLK4 signal at 2 fsymb to clock root Nyquist filters 12A and 12B and interpolation filters 14. A clock generator 22 supplies a clock signal CLK3 at the frequency of sampling rate fsamp to block 16 to control the rate at which it processes the za(n) and zb(n) sequence to produce the DOUT sequence.
Timing synchronizer 24 also supplies an interpolation coefficient μk to interpolation filters 14 controlling how they interpolate between successive elements of the ya(n) and yb(n) sequences. to calculate each element of the za(n) and zb(n) as follows:za(n)=(1−μk)ya(n−1)+μkya(n), andzb(n)=(1−μk)yb(n−1)+μkyb(n).Timing synchronizer 24 increments μk by an amount 1/K at the sampling rate fsamp of the CLK3 signal, and resets μk to 0 on every Kth pulse of the CLK3 signal. Thus μk is the repetitive sequenceμk={0, 1/K, 2/K . . . (K−1)/K, 0, 1/K, . . . }.While the values of ya(n), yb(n), ya(n−1) and yb(n−1) change at the symbol rate frequency 2·fsymb of the CLK4 signal, timing synchronizer 24 changes the value of interpolation coefficient μk at the sample rate fsamp of clock signal CLK3 so that elements of za(n) and zb(n) appear at the input of block 16 at sampling rate fsamp.
Modulator 8 is used in applications in which the data rate fdata at which elements of input sequence DIN are supplied to block 10 may vary but the sampling rate fsamp at which elements of the DOUT sequences are supplied to DAC 18 are to be held constant and independent of data rate fdata. From equations [1] and [2] above it may be seen thatfsamp=(2K/N)fdata  [3]fsamp=2K·fsymb  [4]The value of N is constant ratio between the symbol rate fsymb clock signal CLK2 and the rate fdata of clock signal CLK1N=fdata/fsymb  [5]From equation [4] we see that the value of 2K is the rate ratio between fsymb and fsamp. Since root Nyquist filters 12A and 12B produce sequences ya(n) and yb(n) at frequency 2fsymb, timing synchronizer 24 adjusts the μk sequence supplied as input to interpolation filters 14 so that the filters provide the correct rate ratio K between it's input and output sequences.
FIG. 2 illustrates an example interpolation filter 14 of FIG. 1 for producing the za(n) sequence in response to the ya(n) sequence including a register 26 clocked by the CLK2 signal for storing a current ya(n) value as a next ya(n−1) value, a pair of summers 27 and 28 and a multiplier 30 for processing the ya(n), ya(n−1) and μk sequences to produce the za(n) sequence. A multiplier 30 capable of multiplying elements of the sequence:μk={0, 1/K, 2/K . . . (K−1)/K, 0, 1/K, . . . }is relatively simple and inexpensive to manufacture when K is restricted to values that are integer powers of 2, such that K=2P, where P is an integer. But when K is allowed to be any integer K>1, multiplier 30 becomes more complex and expensive, and when K is allowed to be any number K>1, including fractional numbers, then multiplier 30 becomes very expensive. Sincefdata=(N/2K)fsampand since N and fsamp are fixed, then when we restrict the value of K to integers or powers of two, we also restrict the fdata of the input data sequence DIN to a limited set of allowable values. Thus a variable modulator designer seeking to employ the modulator architecture of FIG. 1 is faced with the choosing between a low cost option wherein fdata is limited to values for which K=2P, a medium cost option wherein fdata is restricted to value for which K is a positive integer, and a high cost option in which K may be any real number, K>=1.
Another drawback to the variable rate modulator architecture of FIG. 1 is that it requires timing synchronizer 24 to generate an additional clock signal CLK2 that is phase locked to clock signal CLK1. Phase locking circuitry is expensive and subjects the CLK2 signal to jitter.
What is needed is a lower cost architecture for a variable rate quadrature amplitude modulator that allows K to be any real number K>=1 and which avoids the need for phase locking circuits.